1. Field
The following description relates to a reconfigurable architecture and a loop scheduling method.
2. Description of Related Art
In general, a reconfigurable architecture is an architecture that can change the hardware configuration of a computing apparatus so that hardware configuration is optimized for a specific task.
Processing a certain task only in hardware presents difficulties in efficiently handling modifications or changes made during processing of the task due to the fixed functionality of the hardware, while processing a certain task only in software can easily deal with modifications or changes made during processing of the task, but results in a low processing speed compared to hardware processing of the task.
The reconfigurable architecture has been designed to obtain all of the advantages of hardware processing and software processing. In particular, the reconfigurable architecture has attracted a lot of attention in a digital signal processing field in which the same tasks are iteratively executed.
A representative reconfigurable architecture is a Coarse-Grained Array (CGA). The CGA is constituted by a plurality of processing units and can be optimized for a specific task by changing connections between the processing units.
It is difficult to quickly obtain an appropriate solution for loop scheduling for a general CGA, so many heuristic algorithms for solving this problem have been developed. The conventional algorithms are based on modulo scheduling to increase utilization of function units of the CGA. In the conventional algorithms, a high utilization of function units can be obtained when the number of function units is small, but when a large number of function units are used, it is difficult to obtain a high utilization of the function units.